Layout Optimization of Complementary FET 6T-SRAM Cell Based on a Universal Methodology Using Sensitivity With Respect to Parasitic - and -Values<i /> <i />-Reference-Cited by-同舟云学术

Layout Optimization of Complementary FET 6T-SRAM Cell Based on a Universal Methodology Using Sensitivity With Respect to Parasitic - and -Values

Published:2022-11 Issue:11 Volume:69 Page:6095-6101

ISSN:0018-9383

Container-title:IEEE Transactions on Electron Devices

language:

Short-container-title:IEEE Trans. Electron Devices

Author:

Luo Yanna¹^ORCID,Cao Lei¹^ORCID,Zhang Qingzhu¹^ORCID,Cao Yu²,Zhang Zhaohao¹^ORCID,Yao Jiaxin¹^ORCID,Yan Gangping¹^ORCID,Zhang Xuexiang¹,Gan Weizhuo¹^ORCID,Huo Jiali¹^ORCID,Xu Haoqing¹^ORCID,Tian Guoliang¹,Bu Weihai³,Wu Yongqin³,Wu Zhenhua¹^ORCID,Yin Huaxiang¹^ORCID

Affiliation:

1. Integrated Circuit Advanced Process R&D Center and Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China
2. Hongzhiwei Technology (Shanghai) Company, Ltd., Shanghai, China
3. Semiconductor Technology Innovation Center (Beijing) Corporation, Beijing, China

Funder

“Strategic Priority Research Program” of the Chinese Academy of Sciences
Joint Development Program of Semiconductor Technology Innovation Center (Beijing) Corporation
National Natural Science Foundation of China
Science and Technology program of Beijing Nova Program
Youth Innovation Promotion Association of the Chinese Academy of Sciences

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/9926983/09906928.pdf?arnumber=9906928

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