Virtual FAB Semiconductor Process Modeling Augmented Vertical Gate All Around Complementary FET Based 6T SRAM Path-Finding
Author:
Affiliation:
1. Institute of Microelectronics,Chinese Academy of Science,Beijing,China,100029
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10531806/10531771/10531984.pdf?arnumber=10531984
Reference6 articles.
1. Vertical device architecture for 5nm and beyond: Device & circuit implications
2. Accurate Simulation of Transistor-Level Variability for the Purposes of TCAD-Based Device-Technology Cooptimization
3. Vertical Sandwich Gate-All-Around Field-Effect Transistors With Self-Aligned High-k Metal Gates and Small Effective-Gate-Length Variation
4. Layout Optimization of Complementary FET 6T-SRAM Cell Based on a Universal Methodology Using Sensitivity With Respect to Parasitic - and -Values
5. Physical Insights on Quantum Confinement and Carrier Mobility in Si, Si0.45Ge0.55, Ge Gate-All-Around NSFET for 5 nm Technology Node
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