Vertical device architecture for 5nm and beyond: Device & circuit implications-Reference-Cited by-同舟云学术

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Vertical device architecture for 5nm and beyond: Device & circuit implications

Published:2015-06 Issue: Volume: Page:
ISSN:
Container-title:2015 Symposium on VLSI Technology (VLSI Technology)
language:
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Author:

Thean A. V-Y,Yakimets D.,Huynh Bao T.,Schuddinck P.,Sakhare S.,Bardon M. Garcia,Sibaja-Hernandez A.,Ciofi I.,Eneman G.,Veloso A.,Ryckaert J.,Raghavan P.,Mercha A.,Mocuta A.,Tokei Z.,Verkest D.,Wambacq P.,De Meyer K.,Collaert N.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7198535/7223619/07223689.pdf?arnumber=7223689

Cited by 40 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Simulation of different structured gate-all-around FETs for 2 nm node;Engineering Research Express;2024-08-07

2. Virtual FAB Semiconductor Process Modeling Augmented Vertical Gate All Around Complementary FET Based 6T SRAM Path-Finding;2024 Conference of Science and Technology for Integrated Circuits (CSTIC);2024-03-17

3. Nanoscale Thermal Transport in Vertical Gate-All-Around Junctionless Nanowire Transistors—Part I: Experimental Methods;IEEE Transactions on Electron Devices;2023-12

4. SkyBridge 2.0: A Fine-grained Vertical 3D-IC Technology for Future ICs;ACM Journal on Emerging Technologies in Computing Systems;2023-10-11

5. Creating the Future with Silicon;Advanced Materials Technologies;2023-06-17

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