Nanoscale Thermal Transport in Vertical Gate-All-Around Junctionless Nanowire Transistors—Part I: Experimental Methods-Reference-Cited by-同舟云学术

Nanoscale Thermal Transport in Vertical Gate-All-Around Junctionless Nanowire Transistors—Part I: Experimental Methods

Published:2023-12 Issue:12 Volume:70 Page:6498-6504
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Mukherjee C.¹^ORCID,Rezgui H.¹,Wang Y.¹,Deng M.¹^ORCID,Kumar A.²,Müller J.²^ORCID,Larrieu G.²^ORCID,Maneux C.¹^ORCID

Affiliation:

1. IMS Laboratory, University of Bordeaux, Bordeaux, France

2. LAAS CNRS, UPR 8001, CNRS, Université of Toulouse, Toulouse, France

Funder

Project FVLLMONTI

European Union’s Horizon 2020 Research and Innovation Program

Laboratoire d’Analyse et d’Architecture des Systèmes (LAAS)-Centre National de la Recherche Scientifique (CNRS) Micro and Nanotechnologies Platform, a member of the Renatech French National Network

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/10328902/10278160.pdf?arnumber=10278160

Reference38 articles.

1. Cryogenic Operation of Junctionless Nanowire Transistors

2. Electronic contribution in heat transfer at metal-semiconductor and metal silicide-semiconductor interfaces

3. High-Temperature Performance of Silicon Junctionless MOSFETs

4. Thermal characterization of silicon nanowires for thermoelectric applications;puyoo,2010

5. Temperature dependence of electronic behaviors in n-type multiple-channel junctionless transistors

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Impacts of quantum confinement effect on threshold voltage and drain-induced barrier lowering effect of junctionless surrounding-gate nanosheet NMOSFET including source/drain depletion regions;Microelectronics Journal;2024-10

2. Investigation of thermal stress effects on subthreshold conduction in nanoscale p-FinFET from Multiphysics perspective;Journal of Applied Physics;2024-03-12

3. Evidence of trapping and electrothermal effects in vertical junctionless nanowire transistors;Solid-State Electronics;2024-01

4. Improving the Performance of Free-pGaN Deep-Ultraviolet Light-Emitting Diodes by Embedding Self-Assembled Ni Nanoparticles Between p-AlGaN/p-Electrode;IEEE Transactions on Electron Devices;2023-12

5. Nanoscale Thermal Transport in Vertical Gate- All-Around Junctionless Nanowire Transistors— Part II: Multiphysics Simulation;IEEE Transactions on Electron Devices;2023-12