Impacts of quantum confinement effect on threshold voltage and drain-induced barrier lowering effect of junctionless surrounding-gate nanosheet NMOSFET including source/drain depletion regions

Author:

Xu LijunORCID,An Linfang,Zhao Jia,He Yulei,Teng Lijuan,Jiang Yuanxing

Publisher

Elsevier BV

Reference36 articles.

1. Nanowire transistors without junctions;Colinge;Nat. Nanotechnol.,2010

2. Quantum effect dependent Modelling of short channel junctionless double gate stack(SC-JL-DG) MOSFET for high frequency analog applications, Microelectron. J;Udar,2023

3. Nanoscale thermal transport in vertical gate-all-around junctionless nanowire transistors—Part I: experimental methods;Mukherjee;IEEE Trans. Electron. Dev.,2023

4. Electro-thermal characteristics of junctionless nanowire gate-all-around transistors using compact thermal conductivity model;Kumar;IEEE Trans. Electron. Dev.,2023

5. Impact of aspect ratio and interface trap charge on the performances of junctionless MOSFET-based adiabatic logic circuit;Ganguli;IEEE Trans. Electron. Dev.,2023

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