Impact of Aspect Ratio and Interface Trap Charge on the Performances of Junctionless MOSFET-Based Adiabatic Logic Circuit
Author:
Affiliation:
1. Department of ECE, Meghnad Saha Institute of Technology, Kolkata, India
2. Department of ECE, Kalyani Government Engineering College, Kalyani, India
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/10328902/10304595.pdf?arnumber=10304595
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5. Nanowire transistors without junctions;colinge;Nature Nanotechnol,2010
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