Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits

Author:

Yang Kexin,Liu Taizhi,Zhang Rui,Kim Dae-Hyun,Milor Linda

Funder

Defence Advanced Research projects Agency

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference25 articles.

1. Breakdown data generation and in-die deconvolution methodology to address BEOL and MOL dielectric breakdown challenges;Chen;Microelectron. Reliab.,2015

2. “Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements,”;Cha,2014

3. System-level modeling of microprocessor reliability degradation due to BTI and HCI;Chen,2014

4. A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET circuits;Wang,2011

5. Negative bias temperature instability and gate oxide breakdown modeling in circuits with die-to-die calibration through power supply and ground signal measurements;Cha,2017

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