1. SRAM stability analysis for different cache configurations due to Bias temperature instability and hot carrier injection;Liu,2016
2. Modeling for SRAM reliability degradation due to gate oxide breakdown with a compact current model;Zhang,2017
3. Modeling of the reliability degradation of a FinFET-based SRAM due to bias temperature instability, hot carrier injection, and gate oxide breakdown;Zhang,2017
4. A novel front-end-of-line (FEOL) and middle-of-line (MOL) time-dependent dielectric breakdown lifetime simulator for FinFET technology;Yang,2018
5. A comprehensive time-dependent dielectric breakdown lifetime simulator for both traditional CMOS and FinFET technology;Yang;IEEE Trans. on Very Large Scale Integration (VLSI) systems,2018