1. Murray F, LeCornec F, Bardy S, Bunel C, Verhoeven J, van den Heuvel E, et al. Silicon-based system-in-package: breakthroughs in miniaturization and nano-integration supported by very high quality passives and system level design tools. In: Mater Res Soc Symp Proc, PR-MS 27.536 NXP-R-MS 27.118, April 19, 2007. vol. 969; 2007, p. 27–35 [Invited].
2. Passive and heterogeneous integration towards a silicon-based system-in-package concept;Roozeboom;Thin Solid Films,2006
3. van Driel WD et al. Combined virtual prototyping and reliability testing based design rules for stacked die system in packages. In: Thermal, mechanical and multi-physics simulation experiments in microelectronics and micro-systems. EuroSime 2007; 2007.
4. van Silfhout RBR et al. Effect of metal layout design on passivation crack occurrence using both experimental and simulation techniques. In: Thermal, mechanical and multi-physics simulation experiments in microelectronics and micro-systems. EuroSime 2004; 2004.
5. A test chip design for detecting thin-film cracking in integrated circuits;Gee;IEEE Trans Compon Pack Manuf Technol Part B: Adv Pack,1994