High robust and cost effective double node upset tolerant latch design for nanoscale CMOS technology-Reference-Cited by-同舟云学术

High robust and cost effective double node upset tolerant latch design for nanoscale CMOS technology

Published:2019-02 Issue: Volume:93 Page:89-97
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Li Hongchen,Xiao Liyi,Li Jie,Qi Chunhua

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference35 articles.

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4. A low power-delay-product and robust isolated-DICE based SEU-tolerant latch circuit design;Wey;Microelectron. J.,2014

5. Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies;Fazeli;IET Comput. Digit. Tech.,2009

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