A Low-Area Overhead and Low-Delay Triple-Node-Upset Self-Recoverable Design Based on Stacked Transistors-Reference-Cited by-同舟云学术

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A Low-Area Overhead and Low-Delay Triple-Node-Upset Self-Recoverable Design Based on Stacked Transistors

Published:2024-06 Issue:2 Volume:24 Page:302-312
ISSN:1530-4388
Container-title:IEEE Transactions on Device and Materials Reliability
language:
Short-container-title:IEEE Trans. Device Mater. Relib.

Author:

Xu Hui¹^ORCID,Li Jiuqi¹^ORCID,Ma Ruijun¹^ORCID,Liang Huaguo²^ORCID,Liu Chaoming¹^ORCID,Wang Senling³^ORCID,Wen Xiaoqing⁴^ORCID

Affiliation:

1. School of Computer Science and Engineering, Anhui University of Science and Technology, Huainan, China

2. School of Microelectronics, Hefei University of Technology, Hefei, China

3. Department of Computer Science, Ehime University, Matsuyama, Ehime, Japan

4. Graduate School of Computer Science and Systems Engineering, Kyushu Institute of Technology, Fukuoka, Japan

Funder

Special Fund for Research on National Major Research Instruments of China

National Natural Science Foundation of China

KAKENHI

JPJSBP

NSFC-JSPS Exchange Program

JSPS Grant-in-Aid for Scientific Research

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/7298/10566496/10496500.pdf?arnumber=10496500

Reference29 articles.

1. High robust and cost effective double node upset tolerant latch design for nanoscale CMOS technology

2. Soft Errors Induced by High-Energy Electrons

3. Fault-avoidance C-element based low overhead and TNU-resilient latch

4. Design and Evaluation of Low-Complexity Radiation Hardened CMOS Latch for Double-Node Upset Tolerance

5. Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction

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1. CQCTL: A Cost-Optimized and Quadruple-Node-Upset Completely Tolerant Latch Design for Safety-Critical Applications;2024 IEEE International Test Conference in Asia (ITC-Asia);2024-08-18

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