Low-Overhead Triple-Node-Upset Self-Recoverable Latch Design for Ultra-Dynamic Voltage Scaling Application-Reference-Cited by-同舟云学术

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Low-Overhead Triple-Node-Upset Self-Recoverable Latch Design for Ultra-Dynamic Voltage Scaling Application

Published:2024-06 Issue:6 Volume:71 Page:2632-2645
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Chen Xin¹^ORCID,Bai Yuxin¹^ORCID,Cai Hao²^ORCID,Zhu Congyi¹,Zhou Xinjie³,Zhang Ying¹^ORCID,Liu Weiqiang¹^ORCID

Affiliation:

1. College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, China

2. National ASIC System Engineering Center, School of Electronic Science and Engineering, Southeast University, Nanjing, China

3. China Electronics Technology Group Corporation No. 58 Research Institute, Wuxi, China

Funder

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/8919/10541300/10494356.pdf?arnumber=10494356

Reference35 articles.

1. Alpha-particle-induced soft errors in dynamic memories

2. LEAP: Layout Design through Error-Aware Transistor Positioning for soft-error resilient sequential cell design

3. A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application

4. Protecting scratchpad memory addresses against soft errors

5. A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application

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