Novel radiation hardened latch design considering process, voltage and temperature variations for nanoscale CMOS technology-Reference-Cited by-同舟云学术

Novel radiation hardened latch design considering process, voltage and temperature variations for nanoscale CMOS technology

Published:2011-12 Issue:12 Volume:51 Page:2086-2092
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Nan Haiqing,Choi Ken

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference14 articles.

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4. Upset hardened memory design for submicron CMOS technology;Calin;IEEE Trans Nucl Sci,1996

5. Omana M, Rossi D, Metra C. Novel transient fault hardened static latch. In: Proceedings 18th international test conference; 2003. p. 886–92.

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