A low power and soft error resilience guard‐gated Quartro‐based flip‐flop in 45 nm CMOS technology-Reference-Cited by-同舟云学术

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A low power and soft error resilience guard‐gated Quartro‐based flip‐flop in 45 nm CMOS technology

Published:2021-03-17 Issue:6 Volume:15 Page:571-580
ISSN:1751-858X
Container-title:IET Circuits, Devices & Systems
language:en
Short-container-title:IET Circuits, Devices & Systems

Author:

Kumar Sabavat Satheesh¹,Sundaram Kumaravel¹,Padmanaban Sanjeevikumar²^ORCID,Holm‐Nielsen Jens Bo²,Blaabjerg Frede³

Affiliation:

1. School of Electronics Engineering Vellore Institute of Technology Vellore India

2. Department of Energy Technology Center for Bioenergy and Green Engineering Aalborg University Esbjerg Denmark

3. Department of Energy Technology Center of Reliable Power Electronics Aalborg University Aalborg Denmark

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/cds2.12052

Reference27 articles.

1. Improving Integrated Circuit Performance Through the Application of Hardness-by-Design Methodology

2. Characterization of Heavy-Ion-Induced Single-Event Effects in 65 nm Bulk CMOS ASIC Test Chips

3. Design and Analysis of SEU Hardened Latch for Low Power and High Speed Applications

4. Reconfigurable Hardened Latch and Flip-Flop for FPGAs

5. Area‐efficient temporally hardened by design flip‐flop circuits;Matush B.I.;IEEE Trans. Nucl. Sci,2010

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