Design, assembly and reliability of large die and fine-pitch Cu/low-k flip chip package-Reference-Cited by-同舟云学术

Design, assembly and reliability of large die and fine-pitch Cu/low-k flip chip package

Published:2010-07 Issue:7 Volume:50 Page:986-994
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Ong Yue Ying,Ho Soon Wee,Vaidyanathan Kripesh,Sekhar Vasarla Nagendra,Jong Ming Chinq,Yak Long Samuel Lim,Wen Sheng Vincent Lee,Wai Leong Ching,Rao Vempati Srinivasa,Ong Jimmy,Ong Xuefen,Zhang Xiaowu,Seung Yoon Uk,Lau John H.,Lim Yeow Kheng,Yeo David,Chan Kai Chong,Yanfeng Zhang,Tan Juan Boon,Sohn Dong Kyun

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference16 articles.

1. A 0.11μm CMOS technology featuring copper and very low k interconnects with high performance and reliability;Takao;Microelectron Reliab,2002

2. Advanced HiCTE flip chip packaging of 90-nm Cu/low-k Chips: underfill novel terminal pad structures and processing optimization;Chungpaoboonpatana;J Electron Mater,2005

3. Packaging effects on reliability of Cu/low-k interconnects;Wang;IEEE Trans Dev Mater Reliab,2003

4. Chip-packaging interaction: a critical concern for Cu/low-k packaging;Wang;Microelectron Reliab,2005

5. 150μm pitch Cu/low-k flip chip packaging with polymer encapsulated dicing line (PEDL) and Cu column interconnects;Yoon;IEEE Trans Adv Packag,2008

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1. Effects of Commercial No-Clean Flux on Reliability of Fine Pitch Flip-Chip Package With Solder Bumps and Copper Pillars;IEEE Transactions on Components, Packaging and Manufacturing Technology;2022-08

2. Constituents and performance of no-clean flux for electronic solder;Microelectronics Reliability;2021-08

3. Solder Joints in PCB Assembly and Semiconductor Packaging;Assembly and Reliability of Lead-Free Solder Joints;2020

4. Structural design guideline to minimize extreme low-k delamination potential in 40nm flip-chip packages;Microelectronics Reliability;2012-11

5. Evolution and outlook of TSV and 3D IC/Si integration;2010 12th Electronics Packaging Technology Conference;2010-12