Drop impact reliability of edge-bonded lead-free chip scale packages-Reference-Cited by-同舟云学术

Drop impact reliability of edge-bonded lead-free chip scale packages

Published:2009-07 Issue:7 Volume:49 Page:761-770
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Farris Andrew,Pan Jianbiao,Liddicoat Albert,Krist Michael,Vickers Nicholas,Toleno Brian J.,Maslyk Dan,Shangguan Dongkai,Bath Jasbir,Willie Dennis,Geiger David A.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference31 articles.

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2. Drop impact reliability testing for lead-free and lead-based soldered IC packages;Chong;Microelectron Reliab,2006

3. Investigations of board-level drop reliability of wafer-level chip-scale packages;Lai;ASME J Electron Packag,2007

4. A methodology for drop performance modeling and application for design optimization of chip-scale packages;Syed;IEEE Trans Electron Packag Manufact,2007

5. Board level drop test and simulation of leaded and lead-free BGA-PCB assembly;Qu;Microelectron Reliab,2007

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