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A Methodology for Drop Performance Modeling and Application for Design Optimization of Chip-Scale Packages

  • Published:2007-01 Issue:1 Volume:30 Page:42-48
  • ISSN:1521-334X
  • Container-title:IEEE Transactions on Electronics Packaging Manufacturing
  • language:
  • Short-container-title:IEEE Trans. Electron. Packag. Manufact.

Author:

Syed Ahmer,Kim Seung Mo,Lin Wei,Kim Jin Young,Sohn Eun Sook,Shin Jae Hyeon

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Industrial and Manufacturing Engineering

Cited by 23 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Reliability of Differently Shaped Solder Joints in Chip Resistor Under Drop Impact;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

2. Leadfree SnAgCu Solder Materials Characterization at High Strain Rates at Low Test Temperatures and Drop and Shock Simulation Using Input-G Method;Journal of Electronic Packaging;2023-11-10

3. A novel shock life model for BGA solder joints based on evolutionary power spectral density;International Journal of Fatigue;2023-10

4. Shock and Vibration Simulation for PBGA Board Assemblies with SAC Solder Interconnects using Non-Linear High Strain Rate Properties;2023 22nd IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm);2023-05-30

5. High Strain Rate Materials Characterization at Low Test Temperatures for Thermally Aged SAC-Q Solder Alloys;2022 21st IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (iTherm);2022-05-31
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