Author:
Zhang Xiaowu,Kripesh Vaidyanathan,Chai T.C.,Tan Teck Chun,Pinjala D.
Subject
Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Reference38 articles.
1. Wafer level chip scale packaging (WL-CSP): an overview;Garrou;IEEE Trans Adv Packaging,2000
2. Wafer-level chip size package (WL-CSP);Topper;IEEE Trans Adv Packaging,2000
3. Simon J. Board level reliability of a wafer level CSP. In: Proceedings of APACK’99 symposium on advances in packaging, Singapore; December 1999. p. 98–105.
4. Board level reliability enhancement for a double-bump wafer level chip scale package;Zhang;IMAPS Trans: J Microelectron Electron Packaging,2004
5. SuperCSP™;Kawahara;IEEE Trans Adv Packaging,2000
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