Board Level Reliability Enhancement for A Double-bump Wafer Level Chip Scale Package
Author:
Zhang Xiaowu1,
Wong E. H.1,
Iyer Mahadevan K.1
Affiliation:
1. Institute of Microelectronics (IME), A*STAR, Singapore, 11 Science Park Road, Singapore Science Park II, Singapore 117685, Tel: (65) 7705423; Fax: (65) 7745747; E-mail:xiaowu@ime.a-star.edu.sg
Abstract
This paper presents a nonlinear finite element analysis on board level solder joint reliability enhancement of a double-bump wafer level chip scale package (CSP). A viscoplastic constitutive relation is adopted for the solders to account for its time and temperature dependence in thermal cycling. The fatigue life of solder joint is estimated by the modified Coffin-Manson equation, which has been verified by experimental results using one of the double-bump wafer level CSP packages as the test vehicle. A series of parametric studies were performed by changing the Sn/Ag inner bump size (UBM pad size and standoff height), the eutectic Sn/Pb external solder joint size (pad size and standoff height), pitch, die thickness, and the encapsulant thickness. The results obtained from the modeling are useful to form design guidelines for board level reliability enhancement of the wafer level CSP packages.
Publisher
IMAPS - International Microelectronics Assembly and Packaging Society
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Electronic, Optical and Magnetic Materials
Cited by
1 articles.
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