Affiliation:
1. National University of Defense Technology (NUDT)
Abstract
Three dimensional finite element models were created utilizing APDL (ANSYS Parametric Design Language) for typical multi-chip BGAP (Ball Grid Array Packages) with different sizes to analyze the structure stress and strain when loading steady thermal loads upon them. Subsequently an improved modeling approach including equivalent beam and critical solder ball joint for simplification was studied and introduced. The Darveaux method based on plastic deformation energy accumulation for predicting fatigue life of solder ball joint under thermal cyclic loading was applied to the improved model for calculation, and effects of main design parameters upon fatigue life were studied accordingly. The numerical results reflected the stress distribution and varying traits of the package, compare of results between improved model and detailed model indicates that the simplified modeling method is quite effective and available for different types of analysis. Methods and results of this paper are of certain reference value for the design and optimization for similar kind of packages.
Publisher
Trans Tech Publications, Ltd.
Reference20 articles.
1. HU YongFang, XUE SongBai, YU ShengLin. FEM analysis of stress and strain in CBGA solder joint with different size under thermal cycle [J]. TRANSACTIONS OF THE CHINA WELDING INSTITUTION, 2005, 26(10): 97-100. (In Chinese).
2. De-Shin Liu, Chin-Yu Ni, Ching-Yang Chen. Integrated design method for flip chip CSP with electrical, thermal and thermo-mechanical qualifications[J]. Finite Elements in Analysis and Design, 2003, 39: 661-667.
3. LI ChangGeng, LIN DanHua, ZHOU JieMin. Thermal reliability analysis of package in PBGA [J]. ELECTRONIC COMPONENTS AND MATERIALS, 2008, 27(1): 65-68. (In Chinese).
4. Taekoo Lee , Jinhyuk Lee, Ilgyu Jung. Finite element analysis for solder ball failures in chip scale Package[J]. Microelectronics Reliability 1998, 38: 1941-(1947).
5. Xiaowu Zhang , Vaidyanathan Kripesh, T.C. Chai, Teck Chun Tan, D. Pinjala. Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP) [J]. Microelectronics Reliability , 2008, 48: 602–610.