Author:
Liu De-Shin,Ni Chin-Yu,Chen Ching-Yang
Subject
Applied Mathematics,Computer Graphics and Computer-Aided Design,General Engineering,Analysis
Reference23 articles.
1. P. Elenius, L. Levine, Comparing flip-chip and wire-bond interconnection technologies. Chip Scale Review, ChipScaleReview.com, 2000, pp. 81–87.
2. Solder bump reliability—issues on bump layout;Alander;IEEE Trans. Adv. Packag.,2000
3. S.F. Popelar, A parametric study of flip chip reliability based on solder fatigue modeling. Proceedings of the IEEE/CPMT International Electronic Manufacturing Technology Symposium, 1997, pp. 299–307.
4. S. Michaelides, S.K. Sitaraman, Effect of material and geometry parameters on the thermal–mechanical reliability of flip-chip assemblies, InterSociety Conference on Thermal Phenomena, 1998, pp. 193–200.
5. Process induced stresses of a flip-chip packaging by sequential processing modeling technique;Wang;J. Electron. Packag. Trans. ASME,1998
Cited by
8 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献