Process Induced Stresses of a Flip-Chip Packaging by Sequential Processing Modeling Technique

Abstract

In this paper, a nonlinear finite element framework was established for processing mechanics modeling of flip-chip packaging assemblies and relevant layered manufacturing. In particular, topological change was considered in order to model the sequential steps during the flip-chip assembly. Geometric and material nonlinearity, which includes the viscoelastic properties of underfill and the viscoplastic properties of solder alloys, were considered. Different stress-free temperatures for different elements in the same model were used to simulate practical manufacturing process-induced thermal residual stress field in the chip assembly. As comparison, two FEM models (processing model and nonprocessing model) of the flip-chip package considered, associated with different processing schemes, were analyzed. From the finite element analysis, it is found that the stresses and deflections obtained from nonprocessing model are generally smaller than those obtained from the processing model due to the negligence of the bonding process-induced residual stresses and warpage. The stress values at the given point obtained from the processing model are about 20 percent higher than those obtained from the nonprocessing model. The deflection values at the given points obtained from the processing model are usually 25 percent higher than those obtained from the nonprocessing model. Therefore, a bigger error may be caused by using nonprocessing model in the analysis of process-induced residual stress field and warpage in the packaging assemblies.