Power Package Typical Assembly Process

Author:

Liu Yong

Publisher

Springer New York

Reference28 articles.

1. Reiche M, Wagner G (2003) Wafer thinning: techniques for ultra-thin wafers. Adv Packag 12(3):29

2. Liu Y, Desbins D, Irving S et al (2006) Systematic evaluation of die thinning application in a power SIP by simulation. In: Proceedings of 56th electronic components and technology conference, San Diego

3. Timoshenko S, Woinowsky-Krieger S (1959) Theory of plates and shells. McGraw-Hill, New York

4. Wu E (2003) Influence of grinding process on semiconductor chip strength. In: Proceedings of 53th electronic components and technology conference, New Orleans

5. Yeh C, Zhou W (1996) Parametric finite element analysis of flip chip reliability. Int J Microcirc Electron Packag 19(2):120–127

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