Wafer-level chip size package (WL-CSP)
Author:
Affiliation:
1. Fraunhofer Inst. of Reliability & Microintegration, Berlin, Germany
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/6040/18369/00846640.pdf?arnumber=846640
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