Tapered Through-Silicon-Via Interconnects for Wafer-Level Packaging of Sensor Devices-Reference-Cited by-同舟云学术

Tapered Through-Silicon-Via Interconnects for Wafer-Level Packaging of Sensor Devices

Published:2010-08 Issue:3 Volume:33 Page:713-721
ISSN:1521-3323
Container-title:IEEE Transactions on Advanced Packaging
language:
Short-container-title:IEEE Trans. Adv. Packag.

Author:

Leib Jüergen¹,Bieck Florian¹,Hansen Ulli¹,Looi Kok-Kheong¹,Ngo Ha-Duong²,Seidemann Volker³,Shariff Dzafir⁴,Studzinski Daniel¹,Suthiwongsunthorn Nathapong⁵,Tan Kenneth¹,Wilke Ralph⁶,Yam Kwong-Loon⁴,Topper Michael⁷

Affiliation:

1. Schott Adv. Packaging, Singapore, Singapore

2. Tech. Univ. Berlin, Berlin, Germany

3. Sensitec GmbH, Mainz, Germany

4. StatsChipPAC, Singapore, Singapore

5. UTAC Ltd., Singapore, Singapore

6. Silicon Microstructures, Inc., Milpitas, CA, USA

7. Fraunhofer IZM, Berlin, Germany

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/6040/5536890/05536911.pdf?arnumber=5536911

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