1. Sub-10nm gate-all-around CMOS nanowire transistors on bulk Si substrate;Li;Tech Dig Symp VLSI Tech,2009
2. Ultra-narrow silicon nanowire gate-all-around CMOS devices: impact of diameter, channel-orientation and low temperature on device performance;Singh;Tech Dig Int Electron Dev Meet,2006
3. Modeling of stress-retarded thermal oxidation of nonplanar silicon structures for realization of nanoscale devices;Ma;IEEE Electron Dev Lett,2010
4. Bended gate-all-around nanowire MOSFET: a device with enhanced carrier mobility due to oxidation-induced tensile stress;Moselund;Tech Dig Int Electron Dev Meet,2007
5. Fabrication of planar silicon nanowires on silicon-on-insulator using stress limited oxidation;Kedzierski;J Vac Sci Technol B,1997