Impact of Process-Induced Inclined Sidewalls On Small Signal Parameters of Silicon Nanowire GAA MOSFET
Author:
Affiliation:
1. Indian Institute of Technology Patna,Dept. of Electrical Engineering,Patna,India
2. School of Electronics Engineering, Vellore Institute of Technology,Vellore,India
Funder
Ministry of Science and Technology (MOST) of Taiwan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10322307/10322308/10322347.pdf?arnumber=10322347
Reference14 articles.
1. Analyses on small-signal parameters and radio-frequency modeling of gate-all-around tunneling field-effect transistors;cho;IEEE Trans Electron Devices,2011
2. Impact of Process-Induced Inclined Sidewalls on Gate-Induced Drain Leakage (GIDL) Current of Nanowire GAA MOSFETs
3. RF performance and small-signal parameter extraction of junctionless silicon nanowire MOSFETs;cho;IEEE Trans Electron Devices,2011
4. Effects of corner angle of trapezoidal and triangular channel cross-sections on electrical performance of silicon nanowire field-effect transistors with semi gate-around structure
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