Impact of Process-Induced Inclined Sidewalls on Gate-Induced Drain Leakage (GIDL) Current of Nanowire GAA MOSFETs-Reference-Cited by-同舟云学术

Impact of Process-Induced Inclined Sidewalls on Gate-Induced Drain Leakage (GIDL) Current of Nanowire GAA MOSFETs

Published:2022-09 Issue:9 Volume:69 Page:4815-4820
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Maniyar Ashraf¹^ORCID,Srinivas P. S. T. N.¹^ORCID,Tiwari Pramod Kumar¹^ORCID,Chang-Liao Kuei-Shu²^ORCID

Affiliation:

1. Department of Electrical Engineering, Indian Institute of Technology Patna, Patna, Bihar, India

2. Department of Engineering and System Science, National Tsing Hua University, Hsinchu, Taiwan

Funder

Department of Science and Technology (DST) of India and the Ministry of Science and Technology (MOST) of Taiwan, through the Program of Cooperation between India and Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/9864631/09848422.pdf?arnumber=9848422

Reference28 articles.

1. Effects of corner angle of trapezoidal and triangular channel cross-sections on electrical performance of silicon nanowire field-effect transistors with semi gate-around structure

2. Study on a Scaling Length Model for Tapered Tri-Gate FinFET Based on 3-D Simulation and Analytical Analysis

3. Subthreshold Modeling of GAA MOSFET Including the Effect of Process-Induced Inclined Sidewalls

4. Impact of Trapezoidal Cross Section on Polarization Sensitivity of SNSPD With Ultranarrow Nanowire

5. Subbreakdown drain leakage current in MOSFET

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