A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32nm node and beyond

Author:

Yasutake Nobuaki,Azuma Atsushi,Ishida Tatsuya,Ohuchi Kazuya,Aoki Nobutoshi,Kusunoki Naoki,Mori Shinji,Mizushima Ichiro,Morooka Tetsu,Kawanaka Shigeru,Toyoshima Yoshiaki

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference7 articles.

1. Ghani T, Armstrong M, Auth C, Bost M, Charvat P, Glass G, et al. A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors. In: IEDM tech dig. 2003. p. 978–80.

2. Mistry K, Armstrong M, Auth C, Cea S, Coan T, Ghami T, et al. Delaying forever: uniaxial strained silicon transistors in a 90nm CMOS technology. In: VLSI tech dig. 2004. p. 50–1.

3. Chidambaram PR, Smith BA, Hall LH, Bu H, Chakravarthi S, Kim Y, et al. 35% drive current improvement from recessed-SiGe drain extension on 37nm gate length PMOS, In: VLSI tech dig. 2004. p. 48–9.

4. Luo Z, Chong YF, Kim J, Rovedo N, Greene B, Panda S, et al. Design of high performance PFETs with strained Si channel and laser anneal. In: IEDM tech dig. 2005. p. 495–8.

5. Ohta H, Kim Y, Shimamune Y, Sakuma T, Hatada A, Katakami A, et al. High performance 30nm gate bulk CMOS for 45nm node with ∑-shaped SiGe-SD. In: IEDM tech dig. 2005. p. 247–50.

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