1. 50 nm – Gate All Around (GAA) – Silicon On Nothing (SON) – devices: a simple way to co-integration of GAA transistors within bulk MOSFET process;Monfray;VLSI Symp Tech Dig,2002
2. Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack;Ernst;IEDM Tech Dig,2006
3. High-Performance Fully Depleted Silicon Nanowire (Diameter ≤ 5 nm) Gate-All-Around CMOS Devices;Singh;IEEE Electron Dev Lett,2006
4. Novel integration process and performances analysis of low STandby Power (LSTP) 3D multi-channel CMOSFET (MCFET) on SOI with metal/high-K gate stack;Bernard;VLSI Symp Tech Dig,2008
5. Experimental study on carrier transport limiting phenomena in 10 nm width nanowire CMOS transistors;Tachi;IEDM Tech Dig,2009