Analysis of Nanosheet Field-Effect Transistor With Local Bottom Isolation
Author:
Affiliation:
1. Department of Electronic Engineering, Hanyang University, Seoul, South Korea
2. Department of Electrical and Electronics Engineering, Konkuk University, Seoul, South Korea
Funder
National Research Foundation of Korea
Korea Government
National Research and Development Program through NRF
Ministry of Science and ICT
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/16/10508280/10473692.pdf?arnumber=10473692
Reference19 articles.
1. TCAD-Based Assessment of the Lateral GAA Nanosheet Transistor for Future CMOS
2. 3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications
3. Leakage Optimization of the Buried Oxide Substrate of Nanosheet Field-Effect Transistors
4. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
5. Effective Drive Current in Scaled FinFET and NSFET CMOS Inverters
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