High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices-Reference-Cited by-同舟云学术

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High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

Published:2006-05 Issue:5 Volume:27 Page:383-386
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Singh N.,Agarwal A.,Bera L.K.,Liow T.Y.,Yang R.,Rustagi S.C.,Tung C.H.,Kumar R.,Lo G.Q.,Balasubramanian N.,Kwong D.-L.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/55/34143/01626464.pdf?arnumber=1626464

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