Extraction of small-signal equivalent circuit for de-embedding of 3D vertical nanowire transistor-Reference-Cited by-同舟云学术

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Extraction of small-signal equivalent circuit for de-embedding of 3D vertical nanowire transistor

Published:2022-08 Issue: Volume:194 Page:108359
ISSN:0038-1101
Container-title:Solid-State Electronics
language:en
Short-container-title:Solid-State Electronics

Author:

Neckel Wesling Bruno,Deng Marina,Mukherjee Chhandak,de Matos Magali,Kumar Abhishek,Larrieu Guilhem,Trommer Jens,Mikolajick Thomas,Maneux Cristell

Funder

Horizon 2020

ANR

Horizon 2020 Framework Programme

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference8 articles.

1. C. Maneux et al., ‘Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence’, IEEE IEDM, San Francisco, Dec. 11-15, 2021.

2. Compact modeling of 3D vertical junctionless gate-all-around silicon nanowire transistors towards 3D logic design;Mukherjee;Solid-State Electron,2021

3. M. C. A. M. Koolen, J. A. M. Geelen, and M. P. J. G. Versleijen, ‘An improved de-embedding technique for on-wafer high-frequency characterization’, in Proceedings of the 1991 Bipolar Circuits and Technology Meeting, Minneapolis, MN, USA, 1991, pp. 188–191. doi: 10.1109/BIPOL.1991.160985.

4. Sub-15nm gate-all-around field effect transistors on vertical silicon nanowires;Larrieu;Solid-State Electron,2017

5. Equivalent Circuit Model for Si Avalanche Photodetectors Fabricated in Standard CMOS Process;Lee;IEEE Electron Device Lett,2008

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1. Understanding the Substrate Effect on De-embedding Structures Fabricated on SOI Wafers Using Electromagnetic Simulation;2024 IEEE 36th International Conference on Microelectronic Test Structures (ICMTS);2024-04-15

2. 3-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETs;IEEE Journal on Exploratory Solid-State Computational Devices and Circuits;2023-12

3. Nanoscale Thermal Transport in Vertical Gate-All-Around Junctionless Nanowire Transistors—Part I: Experimental Methods;IEEE Transactions on Electron Devices;2023-12

4. Circuit Design Flow dedicated to 3D vertical nanowire FET;2022 IEEE Latin American Electron Devices Conference (LAEDC);2022-07-04

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