Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence

Author:

Maneux C.1,Mukherjee C.1,Deng M.1,Dubourg M.1,Reveil L.1,Bordea G.1,Lecestre A.2,Larrieu G.2,Trommer J.3,Breyer E.T.3,Slesazeck S.3,Mikolajick T.3,Baumgartner O.4,Karner M.4,Pirker D.4,Stanojevic Z.4,Atienza David5,Levisse A.5,Ansaloni G.5,Poittevin A.6,Bosio A.6,Deleruyelle D.6,Marchand C.6,O'Connor I.6

Affiliation:

1. IMS, University of Bordeaux, UMR CNRS 5218, Bordeaux INP,Talence,France

2. LAAS-CNRS, UPR 8001, CNRS, Université de Toulouse,Toulouse,France

3. gGmbH,NaMLab,Dresden,Germany

4. Global TCAD Solutions GmbH,Vienna,Austria

5. EPFL,Lausanne,Switzerland

6. INL, University of Lyon, CNRS UMR 5270, Ecole Centrale de Lyon,Ecully,France

Publisher

IEEE

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2. 3-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETs;IEEE Journal on Exploratory Solid-State Computational Devices and Circuits;2023-12

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5. Single Transistor Analog Building Blocks: Exploiting Back-Bias Reconfigurable Devices;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26

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