Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design
Author:
Affiliation:
1. University of Bordeaux,Bordeaux INP IMS Laboratory,Talence,France
2. Univ. Lyon, ECL, INSA Lyon, CNRS,UCBLCPE Lyon INL,Ecully,France
3. University of Toulouse,LAAS, UPR,Toulouse,France
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10268496/10268469/10268560.pdf?arnumber=10268560
Reference16 articles.
1. Temperature dependence of characteristic parameters of the H-terminated Sn/p-Si(1 0 0);karata?;Schottky contact,2003
2. On the MOSFET Threshold Voltage Extraction by Transconductance and Transconductance-to-Current Ratio Change Methods: Part II—Effect of Drain Voltage
3. Scalable Modeling of Thermal Impedance in InP DHBTs Targeting Terahertz Applications
4. Evidence of Trapping and Electrothermal Effects in Vertical Junctionless Nanowire Transistors;wang;EUROSOI-ULIS,2023
5. Thermal analysis of ultra-thin body device scaling [SOI and FinFet devices]
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