Thermal analysis of ultra-thin body device scaling [SOI and FinFet devices]
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/8960/28396/01269420.pdf?arnumber=1269420
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Electrothermal Modeling of Multi-Nanosheet FETs With Various Layouts;IEEE Transactions on Electron Devices;2024-04
2. Experimental Analysis and Modeling of Self-Heating and Thermal Coupling in 28 nm FD-SOI CMOS Transistors Down to Cryogenic Temperatures;IEEE Transactions on Electron Devices;2024-04
3. Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design;ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC);2023-09-11
4. Device Design Aware and Interface Thermal Resistance Assisted Self-Heating Analysis in Nanosheet FET;2022 IEEE International Conference on Emerging Electronics (ICEE);2022-12-11
5. Investigation of ambient temperature and thermal contact resistance induced self-heating effects in nanosheet FET;Semiconductor Science and Technology;2022-04-12
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