Abstract
Abstract
Self-heating effect (SHE) is a severe issue in advanced nano-scaled devices such as stacked nanosheet field-effect transistors (NS-FET), which raises the device temperature (T
D), that ultimately affects the key electrical characteristics, i.e. threshold voltage (V
T), DIBL, subthreshold slope (SS), I
OFF, I
ON, etc. SHE puts design constraints in the advanced CMOS logic devices and circuits. In this paper, we thoroughly investigated the impact of ambient temperature and interface thermal contact resistance induced-self heating effect in the NS-FET using extensive numerical simulations. The weak electron–phonon coupling, phonon scattering, and the ambient temperature-induced joule energy directly coupled with thermal contact resistance cause the SHE-induced thermal degradation, which increases the device temperature (T
D) and affects the device reliability. The baseline NS-FET is well-calibrated with the experimental data and 3D quantum corrected drift-diffusion coupled hydrodynamic and thermodynamic transport models is used in our TCAD framework to estimate the impact of ambient temperature and interface thermal contact resistance on the device performance. Moreover, we also evaluate the SHE-induced performance comparison of NS-FET with conventional FinFET and found that thermal degradation in NS-FET potentially worsen the electrical characteristics. Thus, a detailed TCAD analysis shows that the ambient temperature and interface thermal contact resistances deteriorate the effective thermal resistance (R
eff) and device performance metrics.
Subject
Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Reference40 articles.
1. Cramming more components onto integrated circuits, reprinted from electronics, volume 38, number 8, April 19, 1965, pp.114 ff.;Moore;IEEE Solid State Circuits Soc. Newsl.,2006
2. FinFET versus gate-all-around nanowire FET: performance, scaling, and variability;Nagy;IEEE J. Electron Devices Soc.,2018
3. Demonstration of a novel tunnel FET with channel sandwiched by drain;Bagga;Semicond. Sci. Technol.,2019
4. Insights into the operation of negative capacitance FinFET for low power logic applications;Jaisawal;Microelectron. J.,2022
5. Process technology for IBM 14-nm processor designs featuring silicon-on-insulator FinFETs;Stiffler;IBM J. Res. Dev.,2018
Cited by
16 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献