Power Reduction by Clock Gating Technique-Reference-Cited by-同舟云学术

Power Reduction by Clock Gating Technique

Published:2015 Issue: Volume:21 Page:631-635
ISSN:2212-0173
Container-title:Procedia Technology
language:en
Short-container-title:Procedia Technology

Author:

Srinivasan Nandita,Prakash Navamitha S.,Shalakha D. ,Sivaranjani D. ,Sri Lakshmi G. Swetha,Sundari B. Bala Tripura

Publisher

Elsevier BV

Subject

General Earth and Planetary Sciences,General Environmental Science

Reference12 articles.

1. Dushyant Kumar Sharma, Effects of Different Clock Gating Techniques on Design, International Journal of Scientific & Engineering Research, Vol. 3, Issue 5, May-2012.

2. JiteshShinde, Dr.S.S. Salankar, Clock Gating –A Power Optimizing Technique for VLSI Circuits, J.L. Chaturvedi College of Engineering, Department of Electronics & Telecommunication Engineering, Nagpur.

3. Dr. Neelam R. Prakash, Akash, Clock Gating for Dynamic Power Reduction in Synchronous Circuits, International Journal of Engineering Trends and Technology (IJETT) – vol. 4, Issue 5- May 2013.

4. Mohammad Asyaeia, Ali Peiravi, Low power wide gates for modern power efficient processors, Integration-the VLSI journal, vol. 47, p. 272-283, 2014.

5. Massimo Alioto, Member, IEEE, and Gaetano Palumbo, Senior Member, IEEE, “NAND/NOR Adiabatic Gates: Power Consumption, Evaluation and Comparison Versus the Fan-In, IEEE transactions on circuits and systems, fundamental theory and applications, vol. 49, no. 9, September 2002.

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