Low power wide gates for modern power efficient processors-Reference-Cited by-同舟云学术

Low power wide gates for modern power efficient processors

Published:2014-03 Issue:2 Volume:47 Page:272-283
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Asyaei Mohammad,Peiravi Ali

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference29 articles.

1. Digital Integrated Circuits, a Design Perspective;Rabaey,2003

2. L. Wang, R. Krishnamurthy, K. Soumyanath, N. Shanbhag, An energy-efficient leakage-tolerant dynamic circuit technique, in: Proceedings of International ASIC/SOC Conference, 2000, pp. 221–225.

3. A novel variation-tolerant keeper architecture for high-performance low-power wide fan-in dynamic OR gates;Dadgour;IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2010

4. Intel Pentium 4 1.4GHz Review, Part 1: Processor Architecture and Platform Overview, 2000, pp. 1–11. Available from: http://www.xbitlabs.com/articles/cpu/display/pentium4-1400-1.html (online article).

5. Novel timing yield improvement circuits for high-performance low-power wide fan-in dynamic or gates;Mostafa;IEEE Transactions on Circuits and Systems,2011

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