Low power wide gates for modern power efficient processors

Author:

Asyaei Mohammad,Peiravi Ali

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference29 articles.

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2. L. Wang, R. Krishnamurthy, K. Soumyanath, N. Shanbhag, An energy-efficient leakage-tolerant dynamic circuit technique, in: Proceedings of International ASIC/SOC Conference, 2000, pp. 221–225.

3. A novel variation-tolerant keeper architecture for high-performance low-power wide fan-in dynamic OR gates;Dadgour;IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2010

4. Intel Pentium 4 1.4GHz Review, Part 1: Processor Architecture and Platform Overview, 2000, pp. 1–11. Available from: http://www.xbitlabs.com/articles/cpu/display/pentium4-1400-1.html (online article).

5. Novel timing yield improvement circuits for high-performance low-power wide fan-in dynamic or gates;Mostafa;IEEE Transactions on Circuits and Systems,2011

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2. VLFF - A Very Low-power Flip-flop with only Two Clock Transistors;2023 IEEE 36th International System-on-Chip Conference (SOCC);2023-09-05

3. Low Leakage Low Power Domino Logic Technique for Wide Fan-In Applications, 40-Bit Tag Comparator;International Journal of Integrated Engineering;2022-06-21

4. Ultra Low-power, Low-energy Static Single-phase Clocked Flip-flop;2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS);2021-11-28

5. Power Efficient Bit Lines: A Succinct Study;Journal of Physics: Conference Series;2021-01-01

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