Author:
Rajalakshmi R.,Sivakumar P.,Devarajan D.,Subhashini G.
Reference18 articles.
1. Power Efficient High-Level Synthesis by Centralized and Fine-Grained Clock Gating
2. Arunraj, P. & Sujatha, H., ‘Design of Sequential Circuit using Data Driven Clock Gating And Multibit Flip-Flop Integration’, in Proceedings of the Third International Conference on Electronics Communication and Aerospace Technology [ICECA 2019], pp. 1195–1199(2019).
3. Donno, M., Macci, E. & Mazzoni, L., ‘Power-aware clock tree planning’, Proc. ACM/IEEE Int. Symp. Physical Design, pp. 138–147(2004).
4. Dushyant Kumar Sharma, ‘Effects of different clock gating techniques on design’, International Journal of Scientific & Engineering Research, vol. 3, no. 5, pp. 1–4(2012).
5. Dushyant Kumar Soni & Ashish Hiradhar, ‘Dynamic power reduction of synchronous digital design by using of efficient clock gating technique’, International Journal of Engineering and Techniques, vol. 1, no. 3, pp. 18–23(2015).