Design of Sequential Circuit Using Data Driven Clock Gating and Multibit Flip-Flop Integration

Author:

Arunraj P,Hiremath Sujatha

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. The Application of MUX in the Realming of Domino Logic, Dynamic Consequently, and Transmission Gates: A Case Study with Performance Calculation;2023 First International Conference on Advances in Electrical, Electronics and Computational Intelligence (ICAEECI);2023-10-19

2. Implementing Logical Shifters: For Funtionality Testing and Performance of Power Analysis;2023 3rd Asian Conference on Innovation in Technology (ASIANCON);2023-08-25

3. Analysis of power in logic circuits using various clock-gating techniques;INTERNATIONAL CONFERENCE ON SMART TECHNOLOGIES AND APPLICATIONS (ICSTA 2022);2023

4. Low-Power Double-Edge Triggered D Flip-Flop Based on the Conditional Discharge Technique;2022 IEEE 22nd International Conference on Communication Technology (ICCT);2022-11-11

5. A new MBFF merging strategy for post-placement power optimization of IoT devices;2021 IEEE/ACS 18th International Conference on Computer Systems and Applications (AICCSA);2021-11

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