Author:
Donno Monica,Macii Enrico,Mazzoni Luca
Cited by
16 articles.
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1. Clock Aware Low Power Placement;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28
2. Implementation of Routing-denser PnR Flow for an Efficient IC Block Level Design;2023 Second International Conference on Trends in Electrical, Electronics, and Computer Engineering (TEECCON);2023-08-23
3. Advanced Reinforcement Learning Solution for Clock Skew Engineering: Modified Q-Table Update Technique for Peak Current and IR Drop Minimization;IEEE Access;2023
4. Analysis of power in logic circuits using various clock-gating techniques;INTERNATIONAL CONFERENCE ON SMART TECHNOLOGIES AND APPLICATIONS (ICSTA 2022);2023
5. Optimal bounded-skew steiner trees to minimize maximum
k
-active dynamic power;Proceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop;2020-11-05