Analytical modeling simulation and characterization of short channel Junctionless Accumulation Mode Surrounding Gate (JLAMSG) MOSFET for improved analog/RF performance

Author:

Trivedi Nitin,Kumar Manoj,Haldar Subhasis,Deswal S.S.,Gupta Mridula,Gupta R.S.

Funder

CSIR

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,General Materials Science

Reference37 articles.

1. Analog/RF performance of Si nanowire MOSFETs and the impact of process variation;Wang;IEEE Trans. Electron Devices,2007

2. Explicit continuous model for double gate and surrounding gate MOSFET;Yu;Electron. Device, IEEE Trans. On.,2007

3. Nanoscale tri-gate MOSFET for Ultra low power applications using high-k dielectrics, Nanoelectronics, 2013;Kumar,2013

4. Modeling of nanoscale gate-all-around MOSFETs;Jimenez;IEEE Electron Device Lett.,2004

5. Gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 15 nm length gate and 4 nm radius nanowires;Yeo,2006

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