Modeling of negative capacitance underlap graded-channel junction accumulation mode junctionless FET in nano-scale regime-Reference-Cited by-同舟云学术

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Modeling of negative capacitance underlap graded-channel junction accumulation mode junctionless FET in nano-scale regime

Published:2024-03 Issue: Volume:187 Page:207756
ISSN:2773-0123
Container-title:Micro and Nanostructures
language:en
Short-container-title:Micro and Nanostructures

Author:

Chattopadhyay Ankush^ORCID

Publisher

Elsevier BV

Reference32 articles.

1. High-temperature performance of silicon junctionless MOSFETs;Lee;IEEE Trans. Electron. Dev.,2010

2. Junctionless multigate field-effect transistor;Lee;Appl. Phys. Lett.,2009

3. A compact model of subthreshold current with source/drain depletion effect for the short-channel junctionless cylindrical surrounding-gate MOSFETs;Xiao;IEEE Trans. Electron. Dev.,2016

4. A short channel double-gate junctionless transistor model including the dynamic channel boundary effect;Xiao;IEEE Trans. Electron. Dev.,2016

5. Symmetric operation in an extended back gate JLFET for scaling to the 5-nm regime considering quantum confinement effects;Sahay;IEEE Trans. Electron. Dev.,2017

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