Analysis of Underlap Tri-Gate FinFET and Its Capacitance Effects for Analog/Radio Frequency Applications

Abstract

Manufacturing ultra-scaled FinFET devices has become a massive obstacle for device engineers. The critical challenge experienced Multi-Gate FETs is process variation; Consequently, devices’ performances are impacted and analyzed for device performance losses due to misalignments of gate locations close to sources and drain edgess (lower regions). FinFET is examined using a 3D mathematical model, the impact of base gate areas on variables such as electric fields, surface channel potentials, subthreshold oscillations, threshold voltages, and drainage-induced barrier reductions and effects beneath coating. 3D simulators validate the outcomes yielded by the model. The advantage of underlap FinFET of streamlining investigates the spacer dielectric material (low k and high k) and its underlapped Gate length using the TCAD simulator.