A 700 V narrow channel nJFET with low pinch-off voltage and suppressed drain-induced barrier lowering effect

Author:

Mao Kun,Qiao Ming,Zhang WenTong,Zhang Bo,Li Zhaoji

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,General Materials Science

Reference16 articles.

1. Analysis and performance of a smart, high-voltage SenseFET;Li;Chin. J. Semicond.,2007

2. High voltage JFET with adjustable pinch-off voltage;Hung;ICSICT,2010

3. A novel double RESURF LDMOS and a versatile JFET device used as internal power supply and current detector for SPIC;Chen;Microelectron. J.,2006

4. Novel partially depleted SOI MOSFET for suppression floating-body effect: an embedded JFET structure;Orouji;Superlattices Microstruct.,2012

5. Commercial SiC device processing: status and requirements with respect to SiC based power devices;Treu;Superlattices Microstruct.,2006

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design of a P-JFET Compatible with CMOS Technology;2022 7th International Conference on Integrated Circuits and Microsystems (ICICM);2022-10-28

2. Study of Low Pinch-Off Voltage JFET in 500V High Voltage Process;2020 China Semiconductor Technology International Conference (CSTIC);2020-06-26

3. A 500-V High ON-BV Parasitic JFET With an Optimized Drift Region;IEEE Transactions on Electron Devices;2019-03

4. Design of a 700 V DB-nLDMOS Based on Substrate Termination Technology;IEEE Transactions on Electron Devices;2015-12

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