Design of a P-JFET Compatible with CMOS Technology
Author:
Affiliation:
1. University of Posts & Telecommunications,school of electronic engineering Xi’an,Xi’an,Shaanxi
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10011216/10011228/10011250.pdf?arnumber=10011250
Reference13 articles.
1. Design and application of a depletion-mode NJFET in a high-voltage BiCMOS process
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3. JFET pinched bootstrap diode (JPBD) without substrate leakage current integration to 120V BCDMOS process[C];kim;Power Semiconductor Devices and ICs (ISPSD) 2013 25th International Symposium on,2013
4. Modeling Statistical Dopant Fluctuations Effect on Threshold Voltage of Scaled JFET Devices
5. Research on precise doping control technology of JFET devices[J];xiaojia;Silicon Valley,0
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