Characterization and modeling of transient device behavior under CDM ESD stress-Reference-Cited by-同舟云学术

Characterization and modeling of transient device behavior under CDM ESD stress

Published:2004-10 Issue:2-3 Volume:62 Page:133-153
ISSN:0304-3886
Container-title:Journal of Electrostatics
language:en
Short-container-title:Journal of Electrostatics

Author:

Willemen J.,Andreini A.,De Heyn V.,Esmark K.,Etherton M.,Gieser H.,Groeseneken G.,Mettler S.,Morena E.,Qu N.,Soppa W.,Stadler W.,Stella R.,Wilkening W.,Wolf H.,Zullino L.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Biotechnology,Electronic, Optical and Magnetic Materials

Reference16 articles.

1. H.A. Gieser, P. Egger, Influence of tester parasitics on “charge device model”—failure thresholds, Proc. EOS/ESD Symp., EOS-16, 1994, pp. 69–84.

2. W. Stadler, K. Esmark, K. Reynders, M. Zubeidat, M. Graf, W. Wilkening, J. Willemen, N. Qu, S. Mettler, M. Etherton, D. Nuernbergk, H. Wolf, H. Gieser, W. Soppa, V. De Heyn, M. Natarajan, G. Groeseneken, E. Morena, R. Stella, A. Andreini, M. Litzenberger, D. Pogany, E. Gornik, C. Foss, A. Konrad, M. Frank, Characterization of test circuits for fast assessment of CDM robustness of I/O stages, Proc. EOS/ESD Symp., EOS-25, 2003, pp. 319–327.

3. S.G. Beebe, Simulation of complete CMOS I/O circuit response to CDM stress, Proc. EOS/ESD Symp., EOS-20, 1998, pp. 259–270.

4. M.P.J. Mergens, W. Wilkening, G. Kiesewetter, S. Mettler, H. Wolf, J. Hieber, W. Fichtner, ESD-level circuit simulation—impact of gate RC-delay on the HBM and CDM behavior, Proc. EOS/ESD Symp., EOS-22, 2000, pp. 446–455.

5. Chip-level charged-device modeling and simulation in CMOS integrated circuits;Lee;IEEE Trans. Comput. -Aided Design Integ. Circuits Syst,2003

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