Author:
Jaesik Lee ,Ki-Wook Kim ,Yoonjong Huh ,Bendix P.,Sung-Mo Kang
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Cited by
12 articles.
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1. Influence of Package Trace Properties on CDM Stress;IEEE Transactions on Device and Materials Reliability;2014-09
2. On the Design of Reliable 3D-ICs Considering Charged Device Model ESD Events During Die Stacking;Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14;2014
3. Application of the latency insertion method (LIM) to the modeling of CDM ESD events;2010 Proceedings 60th Electronic Components and Technology Conference (ECTC);2010-06
4. Repeatability and Stress Level Dependence on ESD-CDM Testing for Microelectronic Components;2008 IEEE International Integrated Reliability Workshop Final Report;2008-10
5. CDM ESD failure modes and VFTLP testing for protection evaluation;2008 9th International Conference on Solid-State and Integrated-Circuit Technology;2008-10