Simulation of complete CMOS I/O circuit response to CDM stress-Reference-Cited by-同舟云学术

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Simulation of complete CMOS I/O circuit response to CDM stress

Published: Issue: Volume: Page:
ISSN:
Container-title:Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347)
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Author:

Beebe S.G.

Publisher

ESD Assoc

Link

http://xplorestaging.ieee.org/ielx4/5944/15886/00737046.pdf?arnumber=737046

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Compact Models for Simulation of On-Chip ESD Protection Networks;IEEE Transactions on Electron Devices;2024-01

2. High abstraction level permutational ESD concept analysis;Microelectronics Reliability;2005-02

3. Characterization and modeling of transient device behavior under CDM ESD stress;Journal of Electrostatics;2004-10

4. Reliability challenges of high performance PD SOI CMOS with ultra-thin gate dielectrics;Solid-State Electronics;2004-10

5. ESD-level circuit simulation impact of interconnect RC-delay on HBM and CDM behavior;Journal of Electrostatics;2002-01

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